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Pause-DR and Pause-IR: The FSM pauses its function here to wait for some external operation.Exit1-DR and Exit1-IR: All parallel-loaded (from the Capture-DR and Capture-IR state) or serial-loaded (from the Shift-DR and Shift IR state) data are held in the Register in this state.For each clock cycle, one data bit is shifted into (or out of) the selected Register through TDI (or TDO). If you refer the Figure 2, when the TAP controller is in this state, it will stay at this state as long as TMS=0. Shift-DR and Shift-IR: In this state, the required test data is loaded (or unloaded) serially into (or from) the corresponding Register.Capture-DR and Capture-IR: In this state, data can be loaded in parallel to the corresponding Register.Select-DR/Scan and Select-IR/Scan: This is a temporary state to allow the test data sequence for the corresponding Register (the IR in Select-IR/Scan state and the selected DR in Select-DR/Scan state) to be initiated.Run-Test/Idle: This is a state in which the FSM is waiting for some test operations to complete.Thus if we don’t have the TRST signal then we can still reset the circuit. Also notice that in whatever state the TAP controller may be at, it will goes back to this state if TMS is set to 1 for 5 consecutive TCK cycles.
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Whenever the TRST (optional) signal is asserted, it goes back to this state. Test-Logic-Reset: It resets the JTAG circuits.A brief description about the different states of the TAP controller –